ICT Annual Symposium - June 2003 "Navigating the Technology Network".

ICT Annual Symposium - "Navigating the Technology Network".
4th June 2003

The 29th Annual Symposium of the Institute of Circuit Technology was held on 4th June 2003 at the Lea Marston Hotel in Warwickshire, and was introduced by Peter Starkey, deputising for ICT Chairman Chris Wall.

The proceedings began with Martin Goosey’s overview of grant-funded projects. He described three: WRAP, ROCWAT and TAZDIS.

The WRAP-funded 25-litre drum recycling investigation had been successfully concluded. The ubiquitous container for proprietary chemicals typically costs £2.00 and contains 1.2 kilograms of high-density polyethylene. An estimated 12 million are manufactured in the UK annually, of which 110,000 are consumed by the PCB industry. Re-use was not practical because of cross-contamination issues, but it had been demonstrated at pilot scale that used drums could be cost-effectively cleaned, granulated, and used as moulding material for applications such as land-drainage pipes and railway sleepers. Investment in infrastructure, and a cross-sectional approach, would be needed to develop the project towards general application.

The ROCWAT project had focused on the development of techniques for the removal of organic contamination from rinse waters, and had reached the reporting stage. A combination of advanced oxidation methods, electrochemical and UV/Ozone, had been shown to be capable of reducing chemical oxygen demand to very low levels, using real examples from PCB manufacturers’ process effluent. The equipment was being scaled up from laboratory model to commercial demonstrator.

Martin then went on to describe a new Sustainable Technology Initiative funded programme known as TAZDIS, being undertaken by a UK consortium headed by Intellect, was aimed at achieving zero discharge from the PCB manufacturing plant, and it had already been demonstrated that very simple techniques of dragout minimisation could lead to substantial improvements.

David Hutt then gave a summary of the research activities of the Interconnection Group at Loughborough University, with particular reference to techniques for low-cost flip-chip assembly, where work had been ongoing since 1997. Using bare, unpackaged chips, FR4 substrates and direct interconnection with solder, the concept potentially offered a very cheap and straightforward solution, but demanded considerable process optimisation. Under-bump metallisation of aluminium terminations had proved difficult initially, but success had been achieved using a double-zincate pre-treatment and a home-brew electroless nickel, developed because stabilisers such as lead acetate or thiourea, present in proprietary electroless nickels, had been shown to cause undesirable effects. Electroless nickel bumps of between 5 and 30 microns thickness, finished with a gold flash, had been evaluated.

The challenges of fine-pitch solder paste printing on silicon, including optimisation of the stencil format and the solder paste, had been tackled in collaboration with Celestica and Multicore. Stencils 100 microns thick, with apertures between 100 and 150 microns, had been used to print on 4-inch wafers, and repeatable results had been achieved at 225 micron pitch on 90 micron pads. Work was proceeding at 100 micron pitch on 60 micron pads, and lead-free solder pastes were being evaluated.

Many substrate considerations had come to light during the project, and certain PCB design features and manufacturing tolerances were seen as limiting factors. Borosilicate glass, 150 microns thick, with laser-machined microvias, tracks and pads filled with conductive paste, was being evaluated as an alternative substrate, dimensionally stable and expansion matched to the silicon.
Separately, work continued on the EPSRC-supported fluxless soldering project, characterising organic coatings, which would evaporate during inert-atmosphere soldering, by wetting-balance measurement after various storage conditions. Fluxless soldering was particularly appropriate for “clean” assembly technologies, for example those used in optoelectronics.

David emphasised how collaboration between universities and industrial partners gave great benefits in keeping projects focused and on the right track. He then described how EPSRC is proposing to set up a new IMRC (Innovative Manufacturing Research Council) specifically for the electronics industry, aimed at putting all funding into major institutions which would act as “virtual centres” for collaborative projects.

Tony Ridler considered factors which determine the justification for the incorporation of embedded passive components into printed circuit boards. In a typical PCB assembly, 90% of the component count is in resistors and capacitors, 29% of the solder joints and 40% of the board area. And 880 billion passive components are consumed annually by the world electronics industry.

There were potential savings to be made in size, cost and reliability, and improvements in signal integrity, by creating components within the bare board.

He reviewed the characteristics of proprietary processes available for creating capacitors, then talked in detail about resistors, beginning by explaining the concept of the dimensionless “ohms per square” parameter. Shipley had chosen a 1000 ohms per square base-line as a good compromise to fulfil a wide range of industry requirements. Their resistive material was a doped platinum thin film, coated on to a copper foil by combustion chemical vapour deposition, and was fabricated using a subtractive method. Because the platinum film was chemically inert, it was etched indirectly by a lift-off technique which attacked the underlying epoxy resin. Reliability and performance targets took into account achievable manufacturing tolerances and power dissipation capability, and for the first time electrostatic discharge became a consideration at bare board level. One barrier to early adoption was the limited availability of suitable CAD tools, particularly since different proprietary processes required different design rules. Cost modelling had indicated that embedded resistors became a cost-effective option once resistor density exceeded between 2 and 4 resistors per square centimetre of board area.

Steve Jones presented his paper entitled "High Resolution Benchmarking of HDI Processes", describing how Invotec had committed to driving their large-panel HDI capabilities and yields towards best-in-class, and how they had monitored and measured their performance.
Founded in 2001as a management buy-out of a division of Viasystems, Invotec had made substantial investment in laser, x-ray and mechanical drills, bonding presses, inner layer manufacture, measuring and test equipment, and improved product flow, in order to address the hard realities of survivability in a European printed circuit industry which had suffered permanent change and would tend in future to trail the rest of the World in investment.
It was inevitable that tracks and holes would get smaller, and that numbers of layers and aspect ratios would increase. The successful European manufacturer would be a designer and manufacturer of technically advanced products and services, capable of consistent high yields on large panels. Steve’s message was that yield alone would not ensure survival and that large panel sizes were key to achieving competitive unit cost. In one example, a saving of 50% in cost per circuit could be achieved simply by manufacturing on 27”x 24” panels instead of 18”x 16”, although precision of registration then overtook integrity of image as the primary yield-limiting factor. He illustrated his calculations with a basic design rule that any feature must be placed within 100 microns of true position with respect to any other feature, which actually involved thinking and working in microns and parts per million.

Even with the best available equipment and materials, it was necessary to use real product to study the dimensional interaction between the design and the process, and to develop meaningful measurement techniques for yield prediction. Numerical models demonstrated how the risk of linear out-of-register could increase dramatically for small changes in design rule, and the more advanced “Dimant” tools analysed non-linear distortions using high resolution optical and x-ray measuring equipment.

It had become clear that although certain stages, for example photo-plotting and multilayer bonding, were known to be significant contributors, there were many other more subtle sources of dimensional change throughout the process which needed to be identified, quantified, and taken into account, the core issue being to understand the error contribution or variation of each process step, and to make improvements “by doing a hundred things 1% better not one thing 100% better”.

After lunch, delegates had the opportunity to visit Invotec’s special products facility in Tamworth, where they were welcomed by Invotec Group Chairman Derrick Bumpsteed, and given an introduction to the company’s history, structure and culture, followed by a conducted tour of the factory.

Pete Starkey
ICT Council